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w wm8750jl stereo codec for portable audio applications wolfson microelectronics plc t o receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews production data, april 2012, rev 4.1 copyright ? 2012 wolfson microelectronics plc description the wm8750jl is a low power, high quality stereo codec designed for portable digi tal audio applications. the device integrates complete interfaces to stereo or mono microphones and a stereo headphone. external component requirements are drastically reduced as no separate microphone or headphone amplifiers are required. advanced on-chip digital signal processing performs graphic equaliser, 3-d sound enhancement and automatic level control for the microphone or line input. the wm8750jl can operate as a master or a slave, with various master clock frequencies including 12 or 24mhz for usb devices, or standard 256f s rates like 12.288mhz and 24.576mhz. different audio sample rates such as 96khz, 48khz, 44.1khz are generated directly from the master clock without the need for an external pll. the wm8750jl operates at supply voltages down to 1.8v, although the digital core can operate at voltages down to 1.42v to save power, and the maximum for all supplies is 3.6 volts. different sections of the chip can also be powered down under software control. the wm8750jl is supplied in a very small and thin 5x5mm qfn package, ideal for use in hand-held and portable systems. features ? dac snr 97db (?a? weighted) , thd -85db at 48khz, 3.3v ? adc snr 88db (?a? weighted) , thd -80db at 48khz, 3.3v ? complete stereo / mono microphone interface - programmable alc (timed out) / noise gate ? on-chip 400mw btl speaker driver (mono) ? on-chip headphone driver - >40mw output power on 16 ? / 3.3v - thd ?73db at 5mw, snr 98db with 16 ? load - no dc blocking capacitors required (capless mode) ? separately mixed mono output ? digital graphic equaliser ? low power - 6 mw stereo playback (1.8v / 1.5v supplies) - 13 mw record & playback (1.8v / 1.5v supplies) ? low supply voltages - analogue 1.8v to 3.6v - digital core: 1.42v to 3.6v - digital i/o: 1.8v to 3.6v ? 256fs / 384fs or usb master clock rates: 12mhz, 24mhz ? audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96khz generated internally from master clock ? 5x5x0.9mm qfn package applications ? portable media player ? mobile phone handsets ? mobile gaming block diagram
wm8750jl production data w pd, april 2012, rev 4.1 2 table of contents description ................................................................................................................... 1 ? features ...................................................................................................................... ... 1 ? applications ................................................................................................................. 1 ? block diag ram ............................................................................................................. 1 ? table of co ntents ..................................................................................................... 2 ? pin config uration ....................................................................................................... 3 ? ordering info rmation .............................................................................................. 3 ? pin descri ption ............................................................................................................ 4 ? absolute maximum ratings ..................................................................................... 5 ? recommended operatio n conditions ................................................................. 5 ? electrical characteristics .................................................................................. 6 ? typical performance ................................................................................................ 8 ? power consumption ............................................................................................................... 8 ? output drivers ................................................................................................................ ........ 9 ? output pga?s linearity ........................................................................................................ 10 ? signal timing re quirements ................................................................................. 11 ? system clock timing ........................................................................................................... . 11 ? audio interface timing ? master mode ......................................................................... 11 ? audio interface timi ng ? slave mode ............................................................................ 12 ? control interface timing ? 3-wire mode ..................................................................... 13 ? control interface timing ? 2-wire mode ..................................................................... 14 ? internal power on reset circuit ...................................................................... 15 ? device description ................................................................................................... 16 ? introduct ion .................................................................................................................. ......... 16 ? input sign al path ............................................................................................................. ...... 16 ? automatic level control (alc) ........................................................................................ 23 ? output sign al path ............................................................................................................ ... 27 ? analogue ou tputs .............................................................................................................. .. 32 ? enabling the outputs .......................................................................................................... 34 ? headphone swit ch .............................................................................................................. .. 34 ? thermal s hutdown .............................................................................................................. . 36 ? headphone output ................................................................................................................ 36 ? digital audio interf ace ...................................................................................................... 37 ? audio interfac e contro l ................................................................................................... 42 ? clocking and sam ple rates .............................................................................................. 44 ? control in terface ............................................................................................................. .. 46 ? power su pplies ................................................................................................................ ...... 47 ? power mana gement .............................................................................................................. 47 ? register map ............................................................................................................... 50 ? digital filter characteristics ........................................................................... 51 ? terminol ogy ................................................................................................................... ......... 51 ? dac filter responses .......................................................................................................... 52 ? adc filter responses .......................................................................................................... 53 ? de-emphasis filt er responses ........................................................................................ 54 ? highpass fi lter ............................................................................................................... ....... 55 ? applications in formation ..................................................................................... 56 ? recommended external componen ts .......................................................................... 56 ? line input conf iguration ................................................................................................... 57 ? microphone input co nfigurati on .................................................................................. 57 ? minimising pop noise at the analogue output s ........................................................ 57 ? power manageme nt examples ......................................................................................... 58 ? important no tice ...................................................................................................... 60 ? address ....................................................................................................................... .............. 60 ? revision hi story ........................................................................................................ 61 ?
production data wm8750jl w pd, april 2012, rev 4.1 3 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8750cjlgefl -25 ? c to +85 ? c 32-lead qfn (5x5x0.9mm) (pb-free) msl1 260 o c wm8750cjlgefl/r -25 ? c to +85 ? c 32-lead qfn (5x5x0.9mm) (pb-free, tape and reel) msl1 260 o c note: reel quantity = 3500
wm8750jl production data w pd, april 2012, rev 4.1 4 pin description pin no name type description 1 mclk digital input master clock 2 dcvdd supply digital core supply 3 dbvdd supply digital buffer (i/o) supply 4 dgnd supply digital ground (return path for both dcvdd and dbvdd) 5 bclk digital input / output audio interface bit clock 6 dacdat digital input dac digital audio data 7 daclrc digital input / output audio interface left / right clock/clock out 8 adcdat digital output adc digital audio data 9 adclrc digital input / output audio interface left / right clock 10 monoout analogue output mono output 11 out3 analogue output analogue output 3 (can be used as headphone pseudo ground) 12 rout1 analogue output right output 1 (line or headphone) 13 lout1 analogue output left output 1 (line or headphone) 14 hpgnd supply supply for analogue output drivers (lout1/2, rout1/2) 15 rout2 analogue output right output 1 (line or headphone or speaker) 16 lout2 analogue output left output 1 (line or headphone or speaker) 17 hpvdd supply supply for analogue output driv ers (lout1/2, rout1/2, monout) 18 avdd supply analogue supply 19 agnd supply analogue ground (return path for avdd) 20 vref analogue output reference voltage decoupling capacitor 21 vmid analogue output midrail voltage decoupling capacitor 22 micbias analogue output microphone bias 23 rinput3 / hpdetect analogue input right channel input 3 or headphone plug-in detection 24 linput3 analogue input left channel input 3 25 rinput2 analogue input right channel input 2 26 linput2 analogue input left channel input 2 27 rinput1 analogue input right channel input 1 28 linput1 analogue input left channel input 1 29 mode digital input control interface selection 30 csb digital input chip select / device address selection 31 sdin digital input/output control interface data input / 2-wire acknowledge output 32 sclk digital input control interface clock input note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
production data wm8750jl w pd, april 2012, rev 4.1 5 absolute maximum ratings absolute maximum ratings are stress ratings only. pe rmanent damage to the device ma y be caused by continuously operating at or beyond these limits. device functional operat ing limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max supply voltages -0.3v +3.63v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -25 ? c +85 ? c storage temperature after soldering -65 ? c +150 ? c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are independent of each other. 3. dcvdd must be less than or equal to avdd and dbvdd. recommended operation conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.42 3.6 v digital supply range (buffer) dbvdd 1.7 3.6 v analogue supplies range avdd, hpvdd 1.8 3.6 v ground dgnd,agnd, hpgnd 0 v
wm8750jl production data w pd, april 2012, rev 4.1 6 electrical characteristics test conditions dcvdd = 1.5v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48k hz, adcosr=1, dacosr=1, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue inputs (linput1, rinput1, linput2, rinput2, linput3, rinput3) to adc out full scale input signal level (for adc 0db input at 0db gain) v infs avdd/3.3 v rms input resistance pins linput1/2/3, rinput1/2/3 pga gain=0db into adc 22 k ? pga gain=+30db into adc 1.5 dc measurement from l/rinput1 16 input pin unused 17 input capacitance 10 pf signal to noise ratio (a-weighted) snr avdd = 3.3v adcosr=1 80 88 db avdd = 3.3v adcosr=0 95 avdd = 1.8v adcosr=1 85 avdd = 1.8v adcosr=0 90 total harmonic distortion thd -1dbfs input, avdd = 3.3v -80 0.01 db % -1dbfs input, avdd = 1.8v -74 0.02 adc channel separation 1khz signal 85 db channel matching 1khz signal -0.5 0.5 db analogue outputs (lout1/2, rout1/2, monoout) 0db full scale output voltage avdd/3.3 vrms mute attenuation 1khz, full scale signal 90 db monoout pin 81 channel separation analogue in to analogue out 85 db dac to line-out (l/rout2 with 10k ? / 50pf load) signal to noise ratio (a-weighted) snr avdd=3.3v 90 97 db avdd=1.8v 94 total harmonic distortion thd avdd=3.3v -85 db avdd=1.8v -79 channel separation 1khz signal 100 db headphone output (lout1/rout1, using capacitors) output power per channel p o output power is very closely correlated with thd; see below. total harmonic distortion plus noise thd+n hpvdd=1.8v, r l =32 ? p o =5mw 0.02 -73 % db hpvdd=1.8v, r l =16 ? p o =5mw 0.03 -70 hpvdd=3.3v, r l =32 ? , p o =5mw 0.015 -76 hpvdd=3.3v, r l =16 ? , p o =5mw 0.02 -73 signal to noise ratio (a-weighted) snr hpvdd = 3.3v 90 98 db hpvdd = 1.8v 93
production data wm8750jl w pd, april 2012, rev 4.1 7 test conditions dcvdd = 1.5v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48k hz, adcosr=1, dacosr=1, pga gain = 0db, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit speaker output (lout2/rout2 with 8 ? bridge tied load, rout2inv=1) output power at 1% thd p o thd = 1% 330 mw (rms) maximum achievable output power p o max avdd=hpvdd=3.3v, r l =8 ? 400 mw (rms) total harmonic distortion thd po=200mw, r l =8 ? , hpvdd=3.3v -60 0.1 db % signal to noise ratio (a-weighted) snr hpvdd=3.3v, r l =8 ? 95 db analogue reference levels midrail reference voltage vmid ?3% avdd/2 +3% v buffered reference voltage vref ?3% avdd/2 +3% v microphone bias bias voltage v micbias 3ma load current ?5% 0.9 ? avdd + 5% v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ ? hz digital input / output input high level v ih 0.7 ? dbvdd v input low level v il 0.3 ? dbvdd v output high level v oh i oh = +1ma 0.9 ? dbvdd v output low level v ol i ol = -1ma 0.1 ? dbvdd v hpdetect (pin 23) input high level v ih 0.7 ? avdd v input low level v il 0.3 ? avdd v
wm8750jl production data w pd, april 2012, rev 4.1 8 typical performance power consumption the power consumption of the wm8750jl depends on the following factors. ? supply voltages: reducing the supply volt ages also reduces supply currents, and t herefore results in significant power savings, especially in the digi tal sections of the wm8750jl. ? oversampling rate: significant power savings can be achieved by running the da c and adc at the lower over-sampling rate of 64 (this is achieved by setting adcosr and dacosr to ?1? in r24). note all figures quoted here assume adcosr=dacosr=1. ? operating mode: disabling parts of the wm8750jl that ar e not currently in use (e.g. mic pre-amps, unused outputs, dac, adc, etc.) also saves power. control register r23 other settings tot. power bit vmidsel vref ainl ainr adcl adcr micb dacl dacr lout1 rout1 lout2 rout2 mono out3 adcosr dacosr vsel vi (ma)vi (ma)vi (ma)vi (ma) mw off 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 11 clocks stopped 3.3 0.000 3.3 0.010 3.3 0.000 3.3 0.000 0.0330 01 2.5 0.000 2.5 0.008 2.5 0.000 2.5 0.000 0.0200 00 1.8 0.000 1.5 0.007 1.8 0.000 1.8 0.000 0.0105 standby 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 11 interface stopped 3.3 0.360 3.3 0.011 3.3 0.000 3.3 0.000 1.2243 (500 kohm vmid string) 01 2.5 0.268 2.5 0.009 2.5 0.000 2.5 0.000 0.6925 00 1.8 0.183 1.5 0.007 1.8 0.000 1.8 0.000 0.3399 playback to line-out 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 11 3.3 2.457 3.3 4.687 3.3 0.250 3.3 0.683 26.6541 01 2.5 1.814 2.5 2.779 2.5 0.178 2.5 0.670 13.6025 00 1.8 1.606 1.5 1.483 1.8 0.122 1.8 0.406 6.0657 playback to 32 ohm headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 11 3.3 2.456 3.3 4.649 3.3 0.250 3.3 0.709 26.6112 01 2.5 1.814 2.5 2.758 2.5 0.178 2.5 0.682 13.5800 00 1.8 1.606 1.5 1.483 1.8 0.122 1.8 0.410 6.0729 playback to 32 ohm headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 11 3.3 2.456 3.3 5.454 3.3 0.250 3.3 1.929 33.2937 0.1mw / channel into load 01 2.5 1.814 2.5 3.354 2.5 0.178 2.5 1.927 18.1825 (jeita cp-2905b) 00 1.8 1.607 1.5 1.831 1.8 0.122 1.8 1.793 9.0861 playback to 32 ohm headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 11 3.3 2.470 3.3 5.469 3.3 0.250 3.3 11.248 64.1421 5mw / channel into load 01 2.5 1.833 2.5 3.408 2.5 0.178 2.5 11.283 41.7550 00 1.8 1.635 1.5 1.862 1.8 0.122 1.8 10.974 25.7088 playback to 32 ohm headphone 01 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 11 r24, out3sw=00 3.3 2.426 3.3 3.969 3.3 0.251 3.3 1.010 25.2648 (capless mode using out3) 01 2.5 1.788 2.5 2.705 2.5 0.179 2.5 0.980 14.1300 00 1.8 1.244 1.5 1.481 1.8 0.122 1.8 0.670 5.8863 playback to 8 ohm btl speaker 01 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 11 r24, rout2inv=1 3.3 2.652 3.3 4.655 3.3 0.250 3.3 1.256 29.0829 01 2.5 1.950 2.5 2.761 2.5 0.178 2.5 1.095 14.9600 00 1.8 1.694 1.5 1.482 1.8 0.122 1.8 0.773 6.8832 headphone amp 01 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 11 clocks stopped 3.3 1.107 3.3 0.624 3.3 0.000 3.3 0.685 7.9728 (line-in to 32 ohm headphone) 01 2.5 0.812 2.5 0.090 2.5 0.000 2.5 0.672 3.9350 00 1.8 0.559 1.5 0.007 1.8 0.000 1.8 0.407 1.7493 speaker amp 01 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 11 clocks stopped 3.3 1.305 3.3 0.565 3.3 0.000 3.3 0.691 8.4513 (line-in to 8 ohm speaker) 01 r24, rout2inv=1 2.5 0.948 2.5 0.092 2.5 0.000 2.5 0.679 4.2975 00 1.8 0.649 1.5 0.007 1.8 0.000 1.8 0.455 1.9977 record from line-in 01 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 11 3.3 4.631 3.3 5.010 3.3 0.273 3.3 0.000 32.7162 01 2.5 3.892 2.5 3.237 2.5 0.196 2.5 0.000 18.3125 00 1.8 3.239 1.5 1.649 1.8 0.135 1.8 0.000 8.5467 record from mono microphone 01 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 11 r32, lmicboost=11; 3.3 2.829 3.3 4.996 3.3 0.273 3.3 0.000 26.7234 01 r23, datsel=01 2.5 2.330 2.5 3.208 2.5 0.194 2.5 0.000 14.3300 00 1.8 1.892 1.5 1.632 1.8 0.134 1.8 0.000 6.0948 record from mono microphone 01 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 11 r32, lmicboost=11; 3.3 3.197 3.3 4.993 3.3 0.273 3.3 0.000 27.9279 (differential) 01 r23, datsel=01; 2.5 2.593 2.5 3.208 2.5 0.194 2.5 0.000 14.9875 00 r32, linsel=11 1.8 2.067 1.5 1.636 1.8 0.134 1.8 0.000 6.4158 stereo record & playback 01 1 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 11 3.3 6.670 3.3 8.014 3.3 0.272 3.3 0.805 52.0113 01 2.5 5.389 2.5 5.326 2.5 0.196 2.5 0.613 28.8100 00 1.8 4.281 1.5 2.851 1.8 0.135 1.8 0.329 12.8175 dbvdd hpvdd r24 r25 (19h) r26 (1ah) avdd dcvdd table 1 supply current consumption notes: 1. all figures are at t a = +25 o c, slave mode, fs = 48khz, mclk = 12.288 mhz (256fs), adcosr=dacosr=1. 2. unless otherwise noted, these measurements ar e quiescent (i.e. signal amplitude is zero).
production data wm8750jl w pd, april 2012, rev 4.1 9 output drivers headphone output power vs thd+n 0.01 0.1 1 10 0.1 1 10 100 power per channel [mw] thd+n [%] avdd=3.3v, 32 ohm load avdd=3.3v, 16 ohm load avdd=1.8v, 32 ohm load avdd=1.8v, 16 ohm load speaker output power vs thd+n 0.01 0.1 1 10 1 10 100 1000 power [mw] thd+n [%] avdd=3.3v, 8 ohm load avdd=1.8v, 8 ohm load notes: 1. these graphs show thd+n relative to the signal am plitude at each point (not relative to full scale). 2. signal frequency = 1khz
wm8750jl production data w pd, april 2012, rev 4.1 10 output pga?s linearity output pga gains -70.000 -60.000 -50.000 -40.000 -30.000 -20.000 -10.000 0.000 10.000 40 50 60 70 80 90 100 110 120 130 xxxvol register setting (binary) measured gain [db] lout1 rout1 lout2 rout2 monoout output pga gain step size 0.000 0.250 0.500 0.750 1.000 1.250 1.500 1.750 2.000 40 50 60 70 80 90 100 110 120 130 xxxvol register setting (binary) step size [db] lout1 rout1 lout2 rout2 monoout
production data wm8750jl w pd, april 2012, rev 4.1 11 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions clkdiv2=0 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 21 ns mclk system clock pulse width low t mclkh 21 ns mclk system clock cycle time t mclky 54 ns mclk duty cycle t mclkds 60:40 40:60 test conditions clkdiv2=1 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 10 ns mclk system clock pulse width low t mclkh 10 ns mclk system clock cycle time t mclky 27 ns audio interface timing ? master mode bclk (output) adcdat adclrc/ daclrc (outputs) t dl dacdat t dda t dht t dst figure 2 digital audio data timing ? master mode (see control interface)
wm8750jl production data w pd, april 2012, rev 4.1 12 test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit bit clock timing information bclk rise time (10pf load) t bclkr 3 ns bclk fall time (10pf load) t bclkf 3 ns bclk duty cycle (normal mode, bclk = mclk/n) t bclkds 50:50 bclk duty cycle (usb mode, bclk = mclk) t bclkds t mclkds audio data input timing information adclrc/daclrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 40 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing ? slave mode bclk daclrc/ adclrc t bch t bcl t bcy dacdat adcdat t lrsu t ds t lrh t dh t dd figure 3 digital audio data timing ? slave mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns adclrc/daclrc set-up time to bclk rising edge t lrsu 10 ns adclrc/daclrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 10 ns note: bclk period should always be greater than or equal to mclk period.
production data wm8750jl w pd, april 2012, rev 4.1 13 control interface timing ? 3-wire mode csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 4 control interface timing ? 3-wire serial control mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8750jl production data w pd, april 2012, rev 4.1 14 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
production data wm8750jl w pd, april 2012, rev 4.1 15 internal power on reset circuit vdd t1 gnd avdd dcvdd dgnd internal porb power on reset circuit figure 6 internal power on reset circuit schematic the wm8750jl includes an internal power-on-reset circ uit, as shown in figure 6, which is used to reset the digital logic into a default state after pow er up. the power on reset circuit is powered from dcvdd and monitors dcvdd and avdd. it asserts porb low if dcvdd or avdd are below a minimum threshold. figure 7 typical power-up sequence figure 7 shows a typical power-up sequence. when dcvdd and avdd rise above the minimum thresholds, vpord_dcvdd and vpord_avdd, there is enough voltage for the circuit to guarantee the power on reset is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when dcvdd rises to vpor_dcvdd_on and avdd rises to vpor_avdd_on, porb is released high and all registers are in thei r default state and writes to the control interface may take place. if dcvdd and avdd rise at diffe rent rates then porb will only be released when dcvdd and avdd have both exceeded the vpor _dcvdd_on and vpor_avdd_on thresholds. on power down, porb is asserted low whenev er dcvdd drops below the minimum threshold vpor_dcvdd_off or avdd drops below the minimum threshold vpor_avdd_off. symbol min typ max unit v pord_dcvdd 0.4 0.6 0.8 v v por_dcvdd_on 0.9 1.26 1.6 v v por_avdd_on 0.5 0.7 0.9 v v por_avdd_off 0.4 0.6 0.8 v table 2 typical por operation (typical values, not tested)
wm8750jl production data w pd, april 2012, rev 4.1 16 device description introduction the wm8750jl is a low power audio codec offeri ng a combination of high quality audio, advanced features, low power and small size. these characte ristics make it ideal for portable digital audio applications such as mp3 and minidisk player / reco rders. stereo 24-bit multi-bit delta sigma adcs and dacs are used with oversampling digita l interpolation and decimation filters. the device includes three stereo analogue inputs that can be switched internally. each can be used as either a line level input or microphone input and linput1/rinput1 and linput2/rinput2 can be configured as mono differential inputs. a programm able gain amplifier with automatic level control (alc) keeps the recording volume constant. t he on-chip stereo adc and dac are of a high quality using a multi-bit, low-order oversampling architectu re to deliver optimum performance with low power consumption. the dac output signal first enters an analogue mi xer where an analogue input and/or the post-alc signal can be added to it. this mix is available on line and headphone outputs. the wm8750jl has a configurable digital audio interface where adc data can be read and digital audio playback data fed to the dac. it supports a number of audio data formats including i 2 s, dsp mode (a burst mode in which frame sync plus 2 data packed words are transmitted), and msb-first, left justified, and can operate in master or slave modes. the wm8750jl uses a unique clocking scheme t hat can generate many commonly used audio sample rates from either a 12.00mhz usb clock or an industry standard 256/384 f s clock. this feature eliminates the common requirement for an external phase-locked loop (pll) in applications where the master clock is not an integer multiple of the sa mple rate. sample rates of 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32k hz, 44.1khz, 48khz, 88. 2khz and 96khz can be generated. the digital filters used for recording and playback ar e optimised for each sampling rate used. to allow full software control over all its features , the wm8750jl offers a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. the design of the wm8750jl has given much attent ion to power consumption without compromising performance. it operates at very low voltages, and includes the ability to power off parts of the circuitry under software control, including standby and power off modes. input signal path the input signal path for each channel consists of a switch to select between three analogue inputs, followed by a pga (programmable gain am plifier) and an optional microphone gain boost. a differential input of either (linput1 ? rinput1) or (linput2 ? rinput2) may also be selected. the gain of the pga can be controlled either by the us er or by the on-chip alc function (see automatic level control). the signal then enters an adc where it is digitised. alternatively, the two channels can also be mixed in the analogue domain and digitised in one adc while the other adc is switched off. the mono-mix signal appears on both digital output channels. signal inputs the wm8750jl has three sets of high impedance, low capacitance ac coupled analogue inputs, linput1/rinput1, linput2/rinput2 and linp ut3/rinput3. inputs can be configured as microphone or line level by enabling or disabling the microphone gain boost. linsel and rinsel control bits (see table 3) are used to select independently between external inputs and internally generated differential products (linput1-rinput1 or linput2-rinput2). the choice of differential signal, linput1-rinput1 or linput2-rinput2 is made using ds (refer to table 5). as an example, the wm8750jl can be set up to convert one differential and one single ended mono signal by applying the differential signal to linput1/rinput1 and the single ended signal to rinput2. by setting linsel to l-r differential (s ee table 3), ds to linput1 ? rinput1 (see table 5) and rinsel to rinput2, each mono signal can then be routed to a separate adc or bypass path.
production data wm8750jl w pd, april 2012, rev 4.1 17 the signal inputs are biased internally to the re ference voltage vref. whenever the line inputs are muted or the device placed into standby mode, the i nputs are kept biased to vref using special anti- thump circuitry. this reduces any audible clicks that may otherwise be heard when changing inputs. dc measurement for dc measurements (for example, battery volt age monitoring), the input signal at the linput1 and/or rinput1 pins can be taken directly in to the respective adc, bypassing both pga and microphone boost. the adc output then becomes unsi gned relative to avdd, instead of being a signed (two?s complement) number relative to vref. setting l/rdcm will override l/rinsel. the input range for dc measurement is agnd to avdd. register address bit label default description r32 (20h) adc signal path control (left) 7:6 linsel 00 left channel input select 00 = linput1 01 = linput2 10 = linput3 11 = l-r differential (either linput1- rinput1 or linput2-rinput2, selected by ds) 5:4 lmicboost 00 left channel microphone gain boost 00 = boost off (bypassed) 01 = 13db boost 10 = 20db boost 11 = 29db boost r33 (21h) adc signal path control (right) 7:6 rinsel 00 right channel input select 00 = rinput1 01 = rinput2 10 = rinput3 11 = l-r differential (either linput1- rinput1 or linput2-rinput2, selected by ds) 5:4 rmicboost 00 right channel microphone gain boost 00 = boost off (bypassed) 01 = 13db boost 10 = 20db boost 11 = 29db boost table 3 input software control register address bit label default description r31 (1fh) adc input mode 5 rdcm 0 right channel dc measurement 0 = normal operation, pga enabled 1 = measure dc level on rinput1 4 ldcm 0 left channel dc measurement 0 = normal operation, pga enabled 1 = measure dc level on linput1 table 4 dc measurement select register address bit label default description r31 (1fh) adc input mode 8 ds 0 differential input select 0: linput1 ? rinput1 1: linput2 ? rinput2 table 5 differential input select
wm8750jl production data w pd, april 2012, rev 4.1 18 mono mixing the stereo adc can operate as a stereo or mono dev ice, or the two channels can be mixed to mono in the analogue domain (i.e. before the adc). monomix selects the mode of operation; either the left or right channel adc can be used, allowing t he unused adc to be powered off or used for a dc measurement conversion. the user also has the flexibility to select the data output from the audio interface using datsel. the default is for le ft and right channel adc data to be output, but the interface may also be configured so that e.g. left channel adc data is output as both left and right data for when mono mixing is selected. note: if dc measurement is selected this overrides the monomix selection. register address bit label default description r31 (1fh) adc input mode 7:6 monomix [1:0] 00 00: stereo 01: analogue mono mix (using left adc) 10: analogue mono mix (using right adc) 11: reserved table 6 mono mixing register address bit label default description r23 (17h) additional control (1) 3:2 datsel [1:0] 00 00: left data=left adc; right data =right adc 01: left data =left adc; right data = left adc 10: left data = right adc; right data =right adc 11: left data = right adc; right data = left adc table 7 adc data output configuration the micbias output provides a low noise refer ence voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external co mponents. the output can be enabled or disables using the micb control bit (see al so the ?power management? section). register address bit label default description r25 (19h) power management (1) 1 micb 0 microphone bias enable 0 = off (high impedance output) 1 = on table 8 microphone bias control the internal micbias circuitry is shown below. note that the is a maximum source current capability for micbias is 3ma. the external biasing resi stors therefore must be large enough to limit the micbias current to 3ma. agnd micbias = 1.8 x vmid = 0.9 x avdd vmid internal resistor internal resistor micb figure 8 microphone bias schematic
production data wm8750jl w pd, april 2012, rev 4.1 19 pga control the pga matches the input signal level to the a dc input range. the pga gain is logarithmically adjustable from +30db to ?17.25db in 0.75db steps. each pga can be controlled either by the user or by the alc function (see automatic level c ontrol). when alc is enabled for one or both channels, then writing to the corresponding pga control register has no effect. the gain is independently adjustable on both right and left line inputs. additionally, by controlling the register bits livu and rivu, the left and right gain settings can be simultaneously updated. setting the lzcen and rzcen bits enables a zero -cross detector which ensures that pga gain changes only occur when the signal is at zero, elimi nating any zipper noise. if zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. this function may be enabled by setting toen in register r23 (17h). the inputs can also be muted in the analogue domai n under software control. the software control registers are shown in table 9. if zero crossi ng is enabled, it is necessary to enable zero cross timeout to un-mute the input pgas. this is bec ause their outputs will not cross zero when muted. alternatively, zero cross can be dis abled before sending the un-mute command. register address bit label default description r0 (00h) left channel pga 8 livu 0 left volume update 0 = store linvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = linvol, right = intermediate latch) 7 linmute 1 left channel input analogue mute 1 = enable mute 0 = disable mute note: livu must be set to un-mute. 6 lzcen 0 left channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately 5:0 linvol [5:0] 010111 ( 0db ) left channel input volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db r1 (01h) right channel pga 8 rivu 0 right volume update 0 = store rinvol in intermediate latch (no gain change) 1 = update left and right channel gains (right = rinvol, left = intermediate latch) 7 rinmute 1 right channel input analogue mute 1 = enable mute 0 = disable mute note: rivu must be set to un-mute. 6 rzcen 0 right channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately 5:0 rinvol [5:0] 010111 ( 0db ) right channel input volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db r23 (17h) additional control (1) 0 toen 0 timeout enable 0 : timeout disabled 1 : timeout enabled table 9 input pga software control
wm8750jl production data w pd, april 2012, rev 4.1 20 analogue to digital converter (adc) the wm8750jl uses a multi-bit, oversampled sigma- delta adc for each channel. the use of multi-bit feedback and high oversampling rates reduces the e ffects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0 volts r.m.s. any voltage greater than full scale may overload the adc and cause distortion. adc digital filter the adc filters perform true 24 bit signal processi ng to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digital filter path is illustrated in figure 9. from adc digital hpf digital filter to digital a udio interface digital decimator a dchpd figure 9 adc digital filter the adc digital filters contain a digital high pass f ilter, selectable via software control. the high-pass filter response is detailed in the digital filter c haracteristics section. when the high-pass filter is enabled the dc offset is continuous ly calculated and subtracted from the input signal. by setting hpor, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. if the dc offset is changed, the stored and subtracted value will not change unless the high-pass filter is enabled. this feature can be used for calibration purposes. in addition the highpass filter may be enabled separately on the left and right channels (see table 11). the output data format can be programmed by the user to accommodate stereo or monophonic recording on both inputs. the polarity of t he output signal can also be changed under software control. the software control is shown in table 10.
production data wm8750jl w pd, april 2012, rev 4.1 21 register address bit label default description r5 (05h) adc and dac control 6:5 adcpol [1:0] 00 00 = polarity not inverted 01 = l polarity invert 10 = r polarity invert 11 = l and r polarity invert 4 hpor 0 store dc offset when high-pass filter disabled 1 = store offset 0 = clear offset 0 adchpd 0 adc high-pass filter enable (digital) hpflren = 0 1 = disable high-pass filter on left and right channels 0 = enable high-pass filter on left and right channels hpflren = 1 0 = high-pass enabled on left, disabled on right 1 = high-pass enabled on right, disabled on left r27 (1bh) 5 hpflren 0 adc high-pass filter left or right enable 0 = high-pass filter enable/disable on left and right channels controlled by adchpd 1 = high-pass filter enabled on left or right channel, as selected by adchpd table 10 adc signal path control hpflren adchpd high pass mode 0 0 high-pass filter enabled on left and right channels 0 1 high-pass filter disabled on left and right channels 1 0 high-pass filter enabled on left channel, disabled on right channel 1 1 high-pass filter disabled on left channel, enabled on right channel table 11 adc high pass filter enable modes
wm8750jl production data w pd, april 2012, rev 4.1 22 digital adc volume control the output of the adcs can be digitally amplified or attenuated over a range from ?97db to +30db in 0.5db steps. the volume of each channel can be cont rolled separately. the gai n for a given eight-bit code x is given by: 0.5 ? (x-195) db for 1 ? x ? 255; mute for x = 0 the lavu and ravu control bits control the loading of digital volume control data. when lavu or ravu are set to 0, the ladcvol or radcvol cont rol data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when either lavu or ravu are set to 1. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r21 (15h) left adc digital volume 7:0 ladcvol [7:0] 11000011 ( 0db ) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db 8 lavu 0 left adc volume update 0 = store ladcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ladcvol, right = intermediate latch) r22 (16h) right adc digital volume 7:0 radcvol [7:0] 11000011 ( 0db ) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db 8 ravu 0 right adc volume update 0 = store radcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = radcvol) table 12 adc digital volume control
production data wm8750jl w pd, april 2012, rev 4.1 23 automatic level control (alc) the wm8750jl has an automatic level control that aims to keep a constant recording volume irrespective of the input signal le vel. this is achieved by continuous ly adjusting the pga gain so that the signal level at the adc input remains constan t. a digital peak detector monitors the adc output and changes the pga gain if necessary. note that when the alc function is enabled, the settings of registers 0 and 1 (linvol, livu, lizc, linmute, rinvol, rivu, rizc and rinmute) are ignored. a selectable zero-cross function ensures that the alc volume updates will be timed to coincide with a zero-crossing of the audio signal. hold time decay time attack time input signal signal after alc pga gain alc target level figure 10 alc operation the alc function is enabled using the alcsel cont rol bits. when enabled, the recording volume can be programmed between ?6db and ?28.5db (relative to a dc full scale) using the alcl register bits. an upper limit for the pga gain can be impos ed by setting the maxgain control bits. hld, dcy and atk control the hold, decay and attack times, respectively: hold time is the time delay between the peak le vel detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold ti me can also be set to zero. the hold time only applies to gain ramp-up, there is no delay befor e ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it ta kes for the pga gain to ramp up across 90% of its range (e.g. from ?15b up to 27.75db). the time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the decay time. the decay time can be programmed in power-of-two (2 n ) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from 27.75db down to -15b gain). the time it takes for the recording level to return to its target value therefore depends on both the atta ck time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than t he attack time. the attack time can be programmed in power-of-two (2 n ) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. when operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register. when one adc channel is unused or used for dc measurement, the peak detector disregards that channel. the alc function can also operate when t he two adc outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the adcs.
wm8750jl production data w pd, april 2012, rev 4.1 24 register address bit label default description r17 (11h) alc control 1 8:7 alcsel [1:0] 00 (off) alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that linvol and rinvol settings (reg. 0 and 1) are the same before entering this mode. 6:4 maxgain [2:0] 111 (+30db) set maximum gain of pga 111 : +30db 110 : +24db ?.(-6db steps) 001 : -6db 000 : -12db 3:0 alcl [3:0] 1011 (-12db) alc target ? sets signal level at adc input 0000 = -28.5db fs 0001 = -27.0db fs ? (1.5db steps) 1110 = -7.5db fs 1111 = -6db fs r18 (12h) alc control 2 7 alczc 0 (zero cross off) alc zero cross detect 0 = change gain immediately 1 = change gain on zero cross only 3:0 hld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s r19 (13h) alc control 3 7:4 dcy [3:0] 0011 (192ms) alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s 3:0 atk [3:0] 0010 (24ms) alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s table 13 alc control note: for correct alc operation in differential input mode it is recommended that the alc is not used with a combined signal gain (mic boost and pga) greater than 30db. alc zero cross the alc zero cross function can be used to ensur e that the alc volume updates will be timed to coincide with a suitable zero-crossing of the audio si gnal. this avoids audible ?z ipper noise? effects of instantaneous volume changes. the alc zero cross f unction includes a timeout to ensure that the gain is updated even if a zero cross does not occur. if the signal level is small, it is possible that a zero cross does not occur, due to dc offset within t he signal path. in this case, the timeout will ensure that the alc volume change is still executed.
production data wm8750jl w pd, april 2012, rev 4.1 25 note that the pga control zero cross function described earlier (see ?input signal path?) also has a timeout function. because the alc function applie s volume changes via a series of small changes, the alc zero cross timeout needs to be many time s faster than the normal, register-controlled pga volume control. this improves the alc response, in particular when handling small signals, where the zero-cross function may be less effective. the alc zero-cross timeout is duration is fixed in relation to mclk. the maximum alc zero-cross timeout period is given by the equation below. in the case of a 12.288mhz mclk, the maximum timeout duration is approximately 21ms. peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is autom atically enabled whenever the alc is enabled. note: if atk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the wm 8750jl has a noise gate function that prevents noise pumping by comparing the signal level at the linput1/2/3 and/or rinput1/2/3 pins against a noise gate threshold, ngth. the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] the adc output can then either be muted or alte rnatively, the pga gain can be held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control r egister. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 1.5db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. note that the noise gate only wor ks in conjunction with the alc function, and always operates on the same channel(s) as t he alc (left, right, both, or none). register address bit label default description r20 (14h) noise gate control 7:3 ngth [4:0] 00000 noise gate threshold 17 -76.5dbfs 17 -75dbfs ? 1.5 db steps 11110 -31.5dbfs 11111 -30dbfs 2:1 ngg [1:0] 00 noise gate type x0 = pga gain held constant 01 = mute adc output 11 = reserved (do not use this setting) 0 ngat 0 noise gate function enable 1 = enable 0 = disable table 14 noise gate control note: the performance of the adc may degrade at high input signal levels if the monitor bypass mux is selected with mic boost and alc enabled.
wm8750jl production data w pd, april 2012, rev 4.1 26 3d stereo enhancement the wm8750jl has a digital 3d enhancement option to artificially increase the separation between the left and right channels. this effect can be us ed for recording or playback, but not for both simultaneously. selection of 3d for record or pl ayback is controlled by register bit mode3d. important: switching the 3d filter from record to playb ack or from playback to record may only be done when adc and dac are disabled. the wm8750jl control interface will only allow mode3d to be changed when adc and dac are disabled (i.e. bits adcl, adcr, dacl and dacr in reg. 26 / 1ah are all zero). the 3d enhancement function is activated by the 3den bit, and has two programmable parameters. the 3ddepth setting controls the degree of ster eo expansion. additionally, one of four filter characteristics can be selected for the 3d proc essing, using the 3dvc and 3dlc control bits. register address bit label default description r16 (10h) 3d enhance 7 mode3d 0 playback/record 3d select 0 = 3d selected for record 1 = 3d selected for playback 6 3duc 0 upper cut-off frequency 0 = high (2.2khz at 48khz sampling) 1 = low (1.5khz at 48khz sampling) 5 3dlc 0 lower cut-off frequency 0 = low (200hz at 48khz sampling) 1 = high (500hz at 48khz sampling) 4:1 3ddepth [3:0] 0000 stereo depth 0000: 0% (minimum 3d effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3d effect) 0 3den 0 3d function enable 1: enabled 0: disabled table 15 3d stereo enhancement function when 3d enhancement is enabled (and/or the graphic equa liser for playback) it may be necessary to attenuate the signal by 6db to avoid limiting. this is a user selectable function, enabled by setting adcdiv2 for the record path and dacdiv2 for the playback path. register address bit label default description r5 (05h) adc and dac control 8 adcdiv2 0 adc 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled 7 dacdiv2 0 dac 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled table 16 adc and dac 6db attenuation select
production data wm8750jl w pd, april 2012, rev 4.1 27 output signal path the wm8750jl output signal paths consist of di gital filters, dacs, analogue mixers and output drivers. the digital filters and dacs are enabled w hen the wm8750jl is in ?playback only? or ?record and playback? mode. the mixers and output driver s can be separately enabled by individual control bits (see analogue outputs). thus it is possi ble to utilise the analogue mixing and amplification provided by the wm8750jl, i rrespective of whether the dacs are running or not. the wm8750jl receives digital input data on the dacda t pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? graphic equaliser and dynamic bass boost ? sigma-delta modulation two high performance sigma-delta audio dacs convert the digital data into two analogue signals (left and right). these can then be mixed with analogue signals from the linput1/2/3 and rinput1/2/3 pins, and the mix is fed to the output driv ers, lout1/rout1, lout2/rout2, out3 and monoout. ? lout1/rout1/out3: can drive a 16 ? or 32 ? stereo headphone or stereo line output. ? lout2/rout2: can drive a 16 ? or 32 ? stereo headphone or stereo line output, or an 8 ? mono speaker. ? monoout: can drive a mono line output or other load down to 10k ? digital dac volume control the signal volume from each dac can be controlled digitally, in the same way as the adc volume (see digital adc volume control). the gain and a ttenuation range is ?127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 ? (x-255) db for 1 ? x ? 255; mute for x = 0 the ldvu and rdvu control bits control the loading of digital volume control data. when ldvu or rdvu are set to 0, the ldacvol or rdacvol cont rol data is loaded into an intermediate register, but the actual gain does not change. both le ft and right gain settings are updated simultaneously when either ldvu or rdvu are set to 1. register address bit label default description r10 (0ah) left channel digital volume 8 ldvu 0 left dac volume update 0 = store ldacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ldacvol, right = intermediate latch) 7:0 ldacvol [7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r11 (0bh) right channel digital volume 8 rdvu 0 right dac volume update 0 = store rdacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rdacvol) 7:0 rdacvol [7:0] 11111111 ( 0db ) right dac digital volume control similar to ldacvol table 17 digital volume control
wm8750jl production data w pd, april 2012, rev 4.1 28 graphic equaliser the wm8750jl has a digital graphic equaliser and adaptive bass boost function. this function operates on digital audio data before it is passed to the audio dacs. bass enhancement can take two different forms: ? linear bass control: bass signals are amplif ied or attenuated by a user programmable gain. this is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. ? adaptive bass boost: the bass volume is am plified by a variable gain. when the bass volume is low, it is boosted more than when the bass volume is high. this method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. treble control applies a user programmable gai n, without any adaptive boost function. bass and treble control are completely independent with separately programmable gains and filter characteristics. register address bit label default description r12 (0ch) bass control 7 bb 0 bass boost 0 = linear bass control 1 = adaptive bass boost 6 bc 0 bass filter characteristic 0 = low cutoff (130hz at 48khz sampling) 1 = high cutoff (200hz at 48khz sampling) 3:0 bass [3:0] 1111 (disabled) bass intensity code bb=0 bb=1 0000 +9db 15 (max) 0001 +9db 14 0010 +7.5db 13 0011 +6db 12 0100 +4.5db 11 0101 +3db 10 0110 +1.5db 9 0111 0db 8 1000 -1.5db 7 1001 -3db 6 1010 -4.5db 5 1011 -6db 4 1100 -6db 3 1101 -6db 2 1110 -6db 1 1111 bypass (off) r13 (0dh) treble control 6 tc 0 treble filter characteristic 0 = high cutoff (8khz at 48khz sampling) 1 = low cutoff (4khz at 48khz sampling) 3:0 trbl [3:0] 1111 (disabled) treble intensity 0000 or 0001 = +9db 0010 = +7.5db ? (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 18 graphic equaliser
production data wm8750jl w pd, april 2012, rev 4.1 29 digital to analogue converter (dac) after passing through the graphic equaliser filters, digital ?de-emphasis? c an be applied to the audio data if necessary (e.g. when the data comes from a cd with pre-emphasis used in the recording). de- emphasis filtering is available for samp le rates of 48khz, 44.1khz and 32khz. the wm8750jl also has a soft mute function, which gradually attenuates the volume of the digital signal to zero. when removed, the gain will return to the original setting. th is function is enabled by default. to play back an audio signal, it must firs t be disabled by setting the dacmu bit to zero. register address bit label default description r5 (05h) adc and dac control 2:1 deemp [1:0] 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis 3 dacmu 1 digital soft mute 1 = mute 0 = no mute (signal active) table 19 dac control the digital audio data is converted to oversampl ed bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs , which convert them to high quality analogue audio signals. the multi-bit da c architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion. in normal operation, the left and right channel di gital audio data is converted to analogue in two separate dacs. however, it is also possible to di sable one channel, so that the same signal (left or right) appears on both analogue output channels. additi onally, there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one dac, while the other dac is switched off. the mono-mix signal can be selected to appear on both analogue output channels. the dac output defaults to non-inverted. setting dacinv will invert the dac output phase on both left and right channels. register address bit label default description r23 (17h) additional control (1) 5:4 dmonomix [1:0] 00 dac mono mix 00: stereo 01: mono ((l+r)/2) into dacl, ?0? into dacr 10: mono ((l+r)/2) into dacr, ?0? into dacl 11: mono ((l+r)/2) into dacl and dacr 1 dacinv 0 dac phase invert 0 : non-inverted 1 : inverted table 20 dac mono mix and phase invert select
wm8750jl production data w pd, april 2012, rev 4.1 30 output mixers the wm8750jl provides the option to mix the da c output signal with analogue line-in signals from the linput1/2/3, rinput1/2/3 pins or a mono diffe rential input (linput1 ? rinput1) or (linput2 ? rinput2), selected by ds (see table 5) . the le vel of the mixed-in signals can be controlled with pgas (programmable gain amplifiers). the mono mixer is designed to allow a number of signal combinations to be mixed, including the possibility of mixing both the right and left channel s together to produce a mono output. to prevent overloading of the mixer when full-scale dac left and right signals are input, the mixer inputs from the dac outputs each have a fixed gain of -6db. the by pass path inputs to the mono mixer have variable gain as determined by r38/r39 bits [6:4]. register address bit label default description r34 (22h) left mixer (1) 2:0 lmixsel 000 left input selection for output mix 000 = linput1 001 = linput2 010 = linput3 011 = left adc input (after pga / micboost) 100 = differential input r36 (24h) right mixer (1) 2:0 rmixsel 000 right input selection for output mix 000 = rinput1 001 = rinput2 010 = rinput3 011 = right adc input (after pga / micboost) 100 = differential input table 21 output mixer signal selection register address bit label default description r34 (22h) left mixer control (1) 8 ld2lo 0 left dac to left mixer 0 = disable (mute) 1 = enable path 7 li2lo 0 lmixsel signal to left mixer 0 = disable (mute) 1 = enable path 6:4 li2lovol [2:0] 101 (-9db) lmixsel signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db r35 (23h) left mixer control (2) 8 rd2lo 0 right dac to left mixer 0 = disable (mute) 1 = enable path 7 ri2lo 0 rmixsel signal to left mixer 0 = disable (mute) 1 = enable path 6:4 ri2lovol [2:0] 101 (-9db) rmixsel signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db table 22 left output mixer control
production data wm8750jl w pd, april 2012, rev 4.1 31 register address bit label default description r36 (24h) right mixer control (1) 8 ld2ro 0 left dac to right mixer 0 = disable (mute) 1 = enable path 7 li2ro 0 lmixsel signal to right mixer 0 = disable (mute) 1 = enable path 6:4 li2rovol [2:0] 101 (-9db) lmixsel signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db r37 (25h) right mixer control (2) 8 rd2ro 0 right dac to right mixer 0 = disable (mute) 1 = enable path 7 ri2ro 0 rmixsel signal to right mixer 0 = disable (mute) 1 = enable path 6:4 ri2rovol [2:0] 101 (-9db) rmixsel signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db table 23 right output mixer control register address bit label default description r38 (26h) mono mixer control (1) 8 ld2mo 0 left dac to mono mixer 0 = disable (mute) 1 = enable path 7 li2mo 0 lmixsel signal to mono mixer 0 = disable (mute) 1 = enable path 6:4 li2movol [2:0] 101 (-9db) lmixsel signal to mono mixer volume 000 = +6db ? (3db steps) 111 = -15db r39 (27h) mono mixer control (2) 8 rd2mo 0 right dac to mono mixer 0 = disable (mute) 1 = enable path 7 ri2mo 0 rmixsel signal to mono mixer 0 = disable (mute) 1 = enable path 6:4 ri2movol [2:0] 101 (-9db) rmixsel signal to mono mixer volume 000 = +6db ? (3db steps) 111 = -15db table 24 mono output mixer control
wm8750jl production data w pd, april 2012, rev 4.1 32 analogue outputs lout1/rout1 outputs the lout1 and rout1 pins can drive a 16 ? or 32 ? headphone or a line output (see headphone output and line output sections, respectively ). the signal volume on lout1 and rout1 can be independently adjusted under software control by writing to lout1vol and rout1vol, respectively. note that gains over 0db may cause clipping if the signal is large. any gain setting below 0101111 (minimum) mutes the output driver. the corresponding output pin remains at the same dc level (the reference voltage on the vref pin), so that no click noise is produced when muting or un- muting. a zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gai n updates. if zero cross is enabled a timeout is also available to update the gain if a zero cro ss does not occur. this function may be enabled by setting toen in register r23 (17h). register address bit label default description r2 (02h) lout1 volume 8 lo1vu 0 left volume update 0 = store lout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = lout1vol, right = intermediate latch) 7 lo1zc 0 left zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 6:0 lout1vol [6:0] 1111001 (0db) lout1 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute r3 (03h) rout1 volume 8 ro1vu 0 right volume update 0 = store rout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rout1vol) 7 ro1zc 0 right zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 6:0 rout1vol [6:0] 1111001 rout1 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute table 25 lout1/rout1 volume control
production data wm8750jl w pd, april 2012, rev 4.1 33 lout2/rout2 outputs the lout2 and rout2 output pins are essentially similar to lout1 and rout1, but they are independently controlled and can also drive an 8 ? mono speaker (see speaker output section). for speaker drive, the rout2 signal must be inverted (rout2inv = 1), so that the left and right channel are mixed to mono in the speaker [l?(-r) = l+r]. register address bit label default description r40 (28h) lout2 volume 6:0 lout2vol [6:0] 1111001 (0db) lout2 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 lo2zc 0 left zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 8 lo2vu 0 left volume update 0 = store lout2vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = lout2vol, right = intermediate latch) r41 (29h) rout2 volume 6:0 rout2vol [6:0] 1111001 (0db) rout2 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 ro2zc 0 right zero cross enable 1 = change gain on zero cross only 0 = change gain immediately 8 ro2vu 0 right volume update 0 = store rout1vol in intermediate latch (no gain change) 1 = update left and right channel gains (left = rout1vol, right = intermediate latch) r24 (18h) additional control (2) 4 rout2inv 0 rout2 invert 0 = no inversion (0 ? phase shift) 1 = signal inverted (180 ? phase shift) table 26 lout2/rout2 volume control mono output the monoout pin can drive a mono line output. the signal volume on monoout can be adjusted under software control by writing to monooutvol. register address bit label default description r42 (2ah) monoout volume 6:0 monoout vol [6:0] 1111001 (0db) monoout volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 mozc 0 monoout zero cross enable 1 = change gain on zero cross only 0 = change gain immediately table 27 monoout volume control
wm8750jl production data w pd, april 2012, rev 4.1 34 out3 output the out3 pin can drive a 16 ? or 32 ? headphone or a line output or be used as a dc reference for a headphone output (see headphone output section). it can be selected to either drive out an inverted rout1 or inverted monoout for e.g. an earpiec e drive between out3 and lout1 or differential output between out3 and monoout. out3 can also drive an un-inverted rout1 signal, which originates at the right mixer output before the output pga. out3sw selects the mode of operation required. register address bit label default description r24 (18h) additional control (2) 8:7 out3sw [1:0] 00 out3 select 00 : vref 01 : rout1 signal (volume controlled by rout1vol) 10 : monoout 11 : right mixer output (no volume control through rout1vol) table 28 out3 select enabling the outputs each analogue output of the wm8750jl can be separ ately enabled or disabl ed. the analogue mixer associated with each output is powered on or off along with the output pin. all outputs are disabled by default. to save power, unused outputs should remain disabled. outputs can be enabled at any time, except when vr ef is disabled (vr=0), as this may cause pop noise (see ?power management? and ?applic ations information? sections) register address bit label default description r26 (1ah) power management (2) 6 lout1 0 lout1 enable 5 rout1 0 rout1 enable 4 lout2 0 lout2 enable 3 rout2 0 rout2 enable 2 mono 0 monoout enable 1 out3 0 out3 enable note: all ?enable? bits are 1 = on, 0 = off table 29 analogue output control whenever an analogue output is disabled, it remains connected to vref (pin 20) through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between vref and each output can be controlled using the vroi bi t in register 27. the default is low (1.5k ? ), so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 40k ? . register address bit label default description r27 (1bh) additional (1) 6 vroi 0 vref to analogue output resistance 0: 1.5 k ? 1: 40 k ? table 30 disabled outputs to vref resistance headphone switch the rinput3/hpdetect pin can be used as a headphone switch control input to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. in this mode, enabled by setting hpswen, hpdetect switches between headphone and speaker outputs (e.g. when the pin is connect ed to a mechanical switch in the headphone socket to detect plug-in). the hpswpol bit reverses the pin?s polarity. note that the lout1, rout1, lout2 and rout2 bits in register 26 must al so be set for headphone and speaker output (see table 31 and table 32).
production data wm8750jl w pd, april 2012, rev 4.1 35 note: when rinput3/hpdetect is used as the hpdetect input, the th resholds become cmos levels (0.3 avdd / 0.7 avdd). hpswen hpswpol hpdetect (pin23) l/rout1 (reg. 26) l/rout2 (reg. 26) headphone enabled speaker enabled 0 x x 0 0 no no 0 x x 0 1 no yes 0 x x 1 0 yes no 0 x x 1 1 yes yes 1 0 0 x 0 no no 1 0 0 x 1 no yes 1 0 1 0 x no no 1 0 1 1 x yes no 1 1 0 0 x no no 1 1 0 1 x yes no 1 1 1 x 0 no no 1 1 1 x 1 no yes table 31 headphone switch operation register address bit label default description r24 (18h) additional control (2) 6 hpswen 0 headphone switch enable 0 : headphone switch disabled 1 : headphone switch enabled 5 hpswpol 0 headphone switch polarity 0 : hpdetect high = headphone 1 : hpdetect high = speaker table 32 headphone switch figure 11 example headset detection circuit using normally-open switch figure 12 example headset detection circuit using normally-closed switch
wm8750jl production data w pd, april 2012, rev 4.1 36 thermal shutdown the speaker and headphone outputs can drive very lar ge currents. to protect the wm8750jl from overheating a thermal shutdown circ uit is included. if the device te mperature reaches approximately 150c and the thermal shutdown circuit is enabled (tsden = 1 ) then the speaker and headphone amplifiers (outputs out1l/r, out2l/r and out3) will be disabled. register address bit label default description r23 (17h) additional control (1) 8 tsden 0 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 33 thermal shutdown headphone output analogue outputs lout1/rout1, lout2/ rout2, and out3, can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitor s, or dc coupled without any capacitor. headphone output using dc blocking capacitors dc coupled headphone output (out3sw = 00) figure 13 recommended headphone output configurations when dc blocking capacitors are used, then thei r capacitance and the load resistance together determine the lower cut-off frequency, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance va lues will diminish the bass response. assuming a 16 ohm load and c1, c2 = 220 ? f: f c = 1 / 2 ? r l c 1 = 1 / (2 ? x 16 ? x 220 ? f) = 45 hz in the dc coupled configuration, the headphone ?ground? is connected to the out3 pin, which must be enabled by setting out3 = 1 and out3sw = 00. as the out3 pin produces a dc voltage of avdd/2 (=vref), there is no dc offset between lout1/rout1 and out3, and therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. it is recommended to connect the dc coupled headphone outputs only to headphones, and not to the line input of another device. although the built-in t hermal shutdown circuit will prevent any damage to the headphone outputs if overloaded, such a connecti on may be noisy, and may not function properly if the other device is grounded. speaker output lout2 and rout2 can differentially drive a mono 8 ? speaker as shown below. lout2 rout2 rout2inv = 1 v spkr = l-(-r) = l+r -1 left mixer right mixer rout2vol lout2vol figure 14 speaker output connection
production data wm8750jl w pd, april 2012, rev 4.1 37 the right channel is inverted by setting the rout2i nv bit, so that the signal across the loudspeaker is the sum of left and right channels. line output the analogue outputs, lout1/rout1 and lout2/rout2, can be used as line outputs. additionally, out3 and monoout can be used as a stereo li ne-out by setting out3sw=11 (reg. 24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35 (left out mix). recommended external components are shown below. figure 15 recommended circuit for line output the dc blocking capacitors and the load resistance together determine the lower cut-off frequency, f c . assuming a 10 kohm load and c1, c2 = 1 ? f: f c = 1 / 2 ? (r l +r 1 ) c 1 = 1 / (2 ? x 10.1k ? x 1 ? f) = 16 hz increasing the capacitance lowers f c , improving the bass response. smaller values of c1 and c2 will diminish the bass response. the function of r1 and r2 is to protect the line outputs from damage when used improperly. digital audio interface the digital audio interface is used for inpu tting dac data into the wm8750jl and outputting adc data from it. it uses five pins: ? adcdat: adc data output ? adclrc: adc data alignment clock ? dacdat: dac data input ? daclrc: dac data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, adclrc and daclrc c an be outputs when the wm8750jl operates as a master, or inputs when it is a slave (see master and slave mode operation, below). four different audio data formats are supported: ? left justified ? i 2 s ? dsp mode all four of these modes are msb first. they are de scribed in audio data formats, below. refer to the electrical characteristic se ction for timing information. master and slave mode operation the wm8750jl can be configured as either a master or slave mode device. as a master device the wm8750jl generates bclk, adclrc and daclrc and thus controls sequencing of the data transfer on adcdat and dacdat. in slave mode, the wm8750jl responds with data to clocks it receives over the digital audio interface. the m ode can be selected by writing to the ms bit (see table 23). master and slave modes are illustrated below.
wm8750jl production data w pd, april 2012, rev 4.1 38 bclk adcdat adclrc dacdat daclrc wm8750jl codec dsp encoder/ decoder note: the adc and dac can run at different sample rates figure 16 master mode figure 17 slave mode note: for optimum adc audio performance in slav e mode, the bclk input signal should be configured to transition at the same time as the falling edge of mclk. the adcdat digital data output is buffered inside t he codec using a digital logic buffering block. however, the adcdat buffering block is not re set by the power-on reset circuit and hence the adcdat pin stage (logic high or logic low) is undefi ned at power up until data is clocked out from the adc. implementation of either of thes e workarounds will ensure correct operation: ? ensure that any external connection to the adcdat pin is made with the understanding that adcdat pin may be driven high or low by the codec until adc data is clocked out. ? tri-state the adcdacdat output pin by setti ng the tri bit in r24 (additional control 2 register). setting this bit will also confi gure adclrc, daclrc and bclk as inputs and (as the codec has no internal pull-up/down resist ors) the input voltage level must be set on these pins by an external source (either t he device connected to the digital audio interface or pull-up/down resistors) to prev ent excess current consumption. audio data formats in i 2 s mode, the msb is available on the second ri sing edge of bclk following a lrclk transition. the other bits up to the lsb are then transmi tted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 18 i 2 s audio interface format (assuming n-bit word length) in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unus ed bclk cycles before each lrclk transition.
production data wm8750jl w pd, april 2012, rev 4.1 39 figure 19 left justified audio interface (assuming n-bit word length)
wm8750jl production data w pd, april 2012, rev 4.1 40 in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a ri sing edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 20 and figure 21. in device slave mode, figure 22 and figure 23, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 20 dsp/pcm mode audio interface (mode a, lrp=0, master) figure 21 dsp/pcm mode audio interface (mode b, lrp=1, master)
production data wm8750jl w pd, april 2012, rev 4.1 41 figure 22 dsp/pcm mode audio interface (mode a, lrp=0, slave) figure 23 dsp/pcm mode audio interface (mode b, lrp=0, slave)
wm8750jl production data w pd, april 2012, rev 4.1 42 audio interface control the register bits controlling audio format, word length and master / slave mode are summarised in table 34. ms selects audio interface operation in master or slave mode. in master mode bclk, adclrc and daclrc are outputs. the frequency of adclrc and daclrc is set by the sample rate control bits sr[4:0] and usb. in sl ave mode bclk, adclrc and daclrc are inputs. register address bit label default description r7 (07h) digital audio interface format 7 bclkinv 0 bclk invert bit (for master and slave modes) 0 = bclk not inverted 1 = bclk inverted 6 ms 0 master / slave mode control 1 = enable master mode 0 = enable slave mode 5 lrswap 0 left/right channel swap 1 = swap left and right dac data in audio interface 0 = output left and right data as normal 4 lrp 0 right, left and i2s modes ? lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity dsp mode ? mode a/b select 1 = msb is available on 1 st bclk rising edge after lrc rising edge (mode b) 0 = msb is available on 2 nd bclk rising edge after lrc rising edge (mode a) 3:2 wl[1:0] 10 audio data word length 11 = 32 bits (see note) 10 = 24 bits 01 = 20 bits 00 = 16 bits 1:0 format[1:0] 10 audio data format select 11 = dsp mode 10 = i 2 s format 01 = left justified 00 = reserved table 34 audio data format control audio interface output tristate register bit tri, register 24(18h) bit[3] can be us ed to tristate the adcdat pin and switch adclrc, daclrc and bclk to inputs. in slave mode (master=0) adclrc, daclrc and bclk are by default configured as inputs and only adcda t will be tri-stated, (see table 35). register address bit label default description r24(18h) additional control (2) 3 tri 0 tristates adcdat and switches adclrc, daclrc and bclk to inputs. 0 = adcdat is an output, adclrc, daclrc and bclk are inputs (slave mode) or outputs (master mode) 1 = adcdat is tristated, adclrc, daclrc and bclk are inputs table 35 tri-stating the audio interface
production data wm8750jl w pd, april 2012, rev 4.1 43 master mode adclrc and daclrc enable in master mode, by default adclrc is disabled when the adc is disabl ed and daclrc is disabled when the dac is disabled. register bit lrcm, regi ster 24(18h) bit[2] changes the control so that the adclrc and daclrc are disabled only when adc and da c are disabled. this enables the user to use e.g. adclrc for both adc and dac lrclk and disable the adc when dac only operation is required, (see table 36). register address bit label default description r24(18h) additional control (2) 2 lrcm 0 selects disable mode for adclrc and daclrc 0 = adclrc disabled when adc (left and right) disabled, da clrc disabled when dac (left and right) disabled. 1 = adclrc and daclrc disabled only when adc (left and right) and dac (left and right) are disabled. table 36 adclrc/daclrc enable bit clock mode the default master mode bit clock generator produces a bit clock frequency based on the sample rate and input mclk frequency as shown in table 40. when enabled by setting the appropriate bcm[1:0] bits, the bit clock mode (bcm) f unction overrides the default mast er mode bit clock generator to produce the bit clock frequency shown in the table below: register address bit label default description r8 (08h) clocking and sample rate control 8:7 bcm[1:0] 00 bclk frequency 00 = bcm function disabled 01 = mclk/4 10 = mclk/8 11 = mclk/16 table 37 master mode bclk frequency control the bcm mode bit clock generator produces 16 or 24 bi t clock cycles per sample. the number of bit clock cycles per sample in this mode is determined by the word length bits (wl[1:0]) in the digital audio interface format register (r7). when these bi ts are set to 00, there will be 16 bit clock cycles per sample. when these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample. please refer to figure 24. the bcm generator uses the adclrc signal, hence the adclrc signal must be enabled when using bit clock mode. to enable the adclrc signal , either the adc must be powered up or, if the adc is not in use, the lrcm bit must be set to enable both the adclrc and daclrc signals when either the adc or the dac is enabled. when the bcm function is enabled, t he following restrictions apply: 1. the bit clock invert (bclki nv) function is not available. 2. the dac and adc must be operated at the same sample rate. 3. dsp late digital audio interface mode is not available and must not be enabled. figure 24 bit clock mode
wm8750jl production data w pd, april 2012, rev 4.1 44 note: the shaded bit clock cycles are present only w hen 24-bit mode is selected. please refer to the ?bit clock mode? description for details. clock output by default adclrc (pin 9) is the adc word clock input/output. under the control of adclrm[1:0], register 27(1bh) bits [8:7] the adclrc pin may be configured as a clock output. if adclrm is 01, 10 or 11 then adclrc pin is always an output even in slave mode or when tri = ?1?, (see table 38). the adc then uses the daclrc pin as it s lrclk in both master and slave modes. register address bit label default description r27(1bh) additional control (3) [8:7] adclrm [1:0] 00 configures adclrc pin 00 = adclrc is adc word clock input (slave mode) or adclrc output (master mode) 01 = adclrc pin is mclk output 10 = adclrc pin is mclk / 5.5 output 11 = adclrc pin is mclk / 6 output table 38 adclrc clock output clocking and sample rates the wm8750jl supports a wide range of master clock frequencies on the mclk pin, and can generate many commonly used audio sample rates directly from the master clock. the adc and dac do not need to run at the same sample rate; se veral different combinations are possible. there are two clocking modes: ? ?normal? mode supports master clocks of 128f s , 192f s , 256f s , 384f s , and their multiples (note: f s refers to the adc or dac sample rate, whichever is faster) ? usb mode supports 12mhz or 24mhz master clocks. this mode is intended for use in systems with a usb interface, and eliminates the need for an external pll to generate another clock frequency for the audio codec. register address bit label default description r8 (08h) clocking and sample rate control 6 clkdiv2 0 master clock divide by 2 1 = mclk is divided by 2 0 = mclk is not divided 5:1 sr [4:0] 00000 sample rate control 0 usb 0 clocking mode select 1 = usb mode 0 = ?normal? mode table 39 clocking and sample rate control the clocking of the wm8750jl is controlled using the clkdiv2, usb, and sr control bits. setting the clkdiv2 bit divides mclk by two interna lly. the usb bit selects between ?normal? and usb mode. each value of sr[4:0] selects one comb ination of mclk divi sion ratios and hence one combination of sample rates (see next page). since all sample rates are generated by dividing mclk, their accuracy depends on the accuracy of mclk. if mclk changes, the sample rates change proportionately. note that some sample rates (e.g. 44.1khz in usb mode) are approximated, i.e. they differ from their target value by a very small amount. this is not audible, as the maximu m deviation is only 0.27% (8.0214khz instead of 8khz in usb mode). by co mparison, a half-tone step corresponds to a 5.9% change in pitch. the sr[4:0] bits must be set to configure the appr opriate adc and dac sample rates in both master and slave mode. note: when the adc is configured at a sample rate of 88.2, 88.235 or 96khz (sr[4:0]), the adc right channel data output will be delayed by one sample relative to the left channel data.
production data wm8750jl w pd, april 2012, rev 4.1 45 mclk clkdiv2=0 mclk clkdiv2=1 adc sample rate (adclrc) dac sample rate (daclrc) usb sr [4:0] filter type bclk (ms=1) ?normal? clock mode (?*? indicates backward compatibility with wm8731) 12.288 mhz 24.576 mhz 8 khz (mclk/1536) 8 khz (mclk/1536) 0 00110 * 1 mclk/4 8 khz (mclk/1536) 48 khz (mclk/256) 0 00100 * 1 mclk/4 12 khz (mclk/1024) 12 khz (mclk/1024) 0 01000 1 mclk/4 16 khz (mclk/768) 16 khz (mclk/768) 0 01010 1 mclk/4 24 khz (mclk/512) 24 khz (mclk/512) 0 11100 1 mclk/4 32 khz (mclk/384) 32 khz (mclk/384) 0 01100 * 1 mclk/4 48 khz (mclk/256) 8 khz (mclk/1536) 0 00010 * 1 mclk/4 48 khz (mclk/256) 48 khz (mclk/256) 0 00000 * 1 mclk/4 96 khz (mclk/128) 96 khz (mclk/128) 0 01110 * 3 mclk/2 11.2896mhz 22.5792mhz 8.0182 khz (mclk/1408) 8.0182 khz (mclk/1408) 0 10110 * 1 mclk/4 8.0182 khz (mclk/1408) 44.1 khz (mclk/256) 0 10100 * 1 mclk/4 11.025 khz (mclk/1024) 11.025 khz (mclk/1024) 0 11000 1 mclk/4 22.05 khz (mclk/512) 22.05 khz (mclk/512) 0 11010 1 mclk/4 44.1 khz (mclk/256) 8.0182 khz (mclk/1408) 0 10010 * 1 mclk/4 44.1 khz (mclk/256) 44.1 khz (mclk/256) 0 10000 * 1 mclk/4 88.2 khz (mclk/128) 88.2 khz (mclk/128) 0 11110 * 3 mclk/2 18.432mhz 36.864mhz 8 khz (mclk/2304) 8 khz (mclk/2304) 0 00111 * 1 mclk/6 8 khz (mclk/2304) 48 khz (mclk/384) 0 00101 * 1 mclk/6 12 khz (mclk/1536) 12 khz (mclk/1536) 0 01001 1 mclk/6 16khz (mclk/1152) 16 khz (mclk/1152) 0 01011 1 mclk/6 24khz (mclk/768) 24 khz (mclk/768) 0 11101 1 mclk/6 32 khz (mclk/576) 32 khz (mclk/576) 0 01101 * 1 mclk/6 48 khz (mclk/384) 48 khz (mclk/384) 0 00001 * 1 mclk/6 48 khz (mclk/384) 8 khz (mclk/2304) 0 00011 * 1 mclk/6 96 khz (mclk/192) 96 khz (mclk/192) 0 01111 * 3 mclk/3 16.9344mhz 33.8688mhz 8.0182 khz (mclk/2112) 8.0182 khz (mclk/2112) 0 10111 * 1 mclk/6 8.0182 khz (mclk/2112) 44.1 khz (mclk/384) 0 10101 * 1 mclk/6 11.025 khz (mclk/1536) 11.025 khz (mclk/1536) 0 11001 1 mclk/6 22.05 khz (mclk/768) 22.05 khz (mclk/768) 0 11011 1 mclk/6 44.1 khz (mclk/384) 8.0182 khz (mclk/2112) 0 10011 * 1 mclk/6 44.1 khz (mclk/384) 44.1 khz (mclk/384) 0 10001 * 1 mclk/6 88.2 khz (mclk/192) 88.2 khz (mclk/192) 0 11111 * 3 mclk/3 usb mode (?*? indicates backward compatibility with wm8731) 12.000mhz 24.000mhz 8 khz (mclk/1500) 8 khz (mclk/1500) 1 00110 * 0 mclk 8 khz (mclk/1500) 48 khz (mclk/250) 1 00100 * 0 mclk 8.0214 khz (mclk/1496) 8.0214khz (mclk/1496) 1 10111 * 1 mclk 8.0214 khz (mclk/1496) 44.118 khz (mclk/272) 1 10101 * 1 mclk 11.0259 khz (mclk/1088) 11.0259khz (mclk/1088) 1 11001 1 mclk 12 khz (mclk/1000) 12 khz (mclk/1000) 1 01000 0 mclk 16khz (mclk/750) 16khz (mclk/750) 1 01010 0 mclk 22.0588khz (mclk/544) 22.0588khz (mclk/544) 1 11011 1 mclk 24khz (mclk/500) 24khz (mclk/500) 1 11100 0 mclk 32 khz (mclk/375) 32 khz (mclk/375) 1 01100 * 0 mclk 44.118 khz (mclk/272) 8.0214khz (mclk/1496) 1 10011 * 1 mclk 44.118 khz (mclk/272) 44.118 khz (mclk/272) 1 10001 * 1 mclk 48 khz (mclk/250) 8 khz (mclk/1500) 1 00010 * 0 mclk 48 khz (mclk/250) 48 khz (mclk/250) 1 00000 * 0 mclk 88.235khz (mclk/136) 88.235khz (mclk/136) 1 11111 * 3 mclk 96 khz (mclk/125) 96 khz (mclk/125) 1 01110 * 2 mclk table 40 master clock and sample rates
wm8750jl production data w pd, april 2012, rev 4.1 46 control interface selection of control mode the wm8750jl is controlled by writing to registers th rough a serial control interface. a control word consists of 16 bits. the fi rst 7 bits (b15 to b9) are address bits t hat select which control register is accessed. the remaining 9 bits (b8 to b0) are dat a bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin selects the interface format. mode interface format low 2 wire high 3 wire table 41 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb latches in a complete control wo rd consisting of the last 16 bits. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sdin sclk csb control register address control register data bits latch figure 25 3-wire serial control interface 2-wire serial control mode the wm8750jl supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the wm8750jl). the wm8750jl operates as a slave dev ice only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bi t, msb first). if the device address received matches the address of the wm8750jl and the r/w bit is ?0?, indicating a write, then the wm8750jl responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1?, the wm8750jl returns to the idle condition and wait for a new start condition and valid address. once the wm8750jl has acknowledged a correct addre ss, the controller sends the first byte of control data (b15 to b8, i.e. the wm8750jl register address plus the first bit of register data). the wm8750jl then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b 7 to b0, i.e. the remaining 8 bits of register data), and the wm8750jl acknowledges again by pulling sdin low. the transfer of data is complete when there is a lo w to high transition on sdin while sclk is high. after receiving a complete address and data sequence the wm8750jl returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 2 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 26 2-wire serial control interface
production data wm8750jl w pd, april 2012, rev 4.1 47 the wm8750jl has two possible device addresses, which can be selected using the csb pin. csb state device address low 0011010 (0 x 34h) high 0011011 (0 x 36h) table 42 2-wire mpu interface address selection power supplies the wm8750jl can use up to four separate power supplies: ? avdd / agnd: analogue supply, powers all analogue functions except the headphone drivers. avdd can range from 1.8v to 3.6v and has t he most significant impact on overall power consumption (except for power consumed in the headphone). a large avdd slightly improves audio quality. ? hpvdd / hpgnd: headphone supply, powers the headphone drivers. hpvdd is normally tied to avdd, but it requires separate layout and dec oupling capacitors to curb harmonic distortion. if hpvdd is lower than avdd, the output signal may be clipped. ? dcvdd: digital core supply, powers all digital functions except the audi o and control interfaces. dcvdd can range from 1.42v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. ? dbvdd: digital buffer supply, powers the audio and control interface buffers. this makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. dbv dd draws much less power than dcvdd, and has no effect on audio quality. dbvdd can range from 1.8v to 3.6v. the return path for dbvdd is dgnd, which is shared with dcvdd. it is possible to use the same supply voltage on all four. however, digital and analogue supplies should be routed and decoupled separatel y to keep digital switching noise out of the analogue signal paths. power management the wm8750jl has two control registers that allow us ers to select which functions are active. for minimum power consumption, unused functions should be di sabled. to avoid any pop or click noise, it is important to enable or dis able functions in the correct order (see applications information). vmidsel is the enable for the vmid reference, which defaults to dis abled and can be enabled as a 50k ? potential divider or, for low power maintenance of vref when all other blocks are disabled, as a 500k ? potential divider.
wm8750jl production data w pd, april 2012, rev 4.1 48 register address bit label default description r25 (19h) power management (1) 8:7 vmidsel 00 vmid divider enable and select 00 ? vmid disabled (for off mode) 01 ? 50k ? divider enabled (for playback/record) 10 ? 500k ? divider enabled (for low-power standby) 11 ? 5k ? divider enabled (for fast start-up) 6 vref 0 vref (necessary for all other functions) 0 = power down 1 = power up 5 ainl 0 analogue in pga left 0 = power down 1 = power up 4 ainr 0 analogue in pga right 0 = power down 1 = power up 3 adcl 0 adc left 0 = power down 1 = power up 2 adcr 0 adc right 0 = power down 1 = power up 1 micb 0 micbias 0 = power down 1 = power up r26 (1ah) power management (2) 8 dacl 0 dac left 0 = power down 1 = power up 7 dacr 0 dac right 0 = power down 1 = power up 6 lout1 0 lout1 output buffer* 0 = power down 1 = power up 5 rout1 0 rout1 output buffer* 0 = power down 1 = power up 4 lout2 0 lout2 output buffer* 0 = power down 1 = power up 3 rout2 0 rout2 output buffer* 0 = power down 1 = power up 2 mono 0 monoout output buffer and mono mixer 0 = power down 1 = power up 1 out3 0 out3 output buffer 0 = power down 1 = power up * the left mixer is enabled when lout1=1 or lout2=1. the right mixer is enabled when rout1=1 or rout2=1. table 43 power management
production data wm8750jl w pd, april 2012, rev 4.1 49 stopping the master clock in order to minimise power consumed in the digi tal core of the wm8750jl, the master clock may be stopped in standby and off modes. if this cannot be done externally at the clock source, the digenb bit (r25, bit 0) can be set to stop the mc lk signal from propagating into the device core. in standby mode, setting digenb will typically prov ide an additional power saving on dcvdd of 20ua. however, since setting digenb has no effect on t he power consumption of other system components external to the wm8750jl, it is pref erable to disable the master clock at its source wherever possible. register address bit label default description r25 (19h) additional control (1) 0 digenb 0 master clock disable 0: master clock enabled 1: master clock disabled table 44 adc and dac oversampling rate selection note: before digenb can be set, the control bits adcl, adcr, dacl and dacr must be set to zero and a waiting time of 1ms must be observed. any failure to follow this procedure may prevent dacs and adcs from re-starting correctly. saving power by reducing oversampling rate the default mode of operation of the adc and dac di gital filters is in 128x oversampling mode. under the control of adcosr and dacosr the oversampling rate may be halved. this will result in a slight decrease in noise performance but will also reduce the power consumption of the device. in usb mode adcosr must be set to 0, i.e. 128x oversampling. register address bit label default description r24 (18h) additional control (2) 1 adcosr 0 adc oversample rate select 1 = 64x (lowest power) 0 = 128x (best snr) 0 dacosr 0 dac oversample rate select 1 = 64x (lowest power) 0 = 128x (best snr) table 45 adc and dac oversampling rate selection adcosr set to ?1?, 64x oversample m ode, is not supported in usb mode (usb=1). saving power at higher supply voltages the analogue supplies to the wm8750jl can run from 1.8v to 3.6v. by default, all analogue circuitry on the device is optimized to run at 3.3v. this se t-up is also good for all other supply voltages down to 1.8v. at lower voltages, performance can be improved by increasing the bias current. if low power operation is preferred the bias current can be left at the default setting. this is controlled as shown below. register address bit label default description r23 (17h) additional control(1) 7:6 vsel [1:0] 11 analogue bias optimization 00: highest bias current, optimized for avdd=1.8v 01: bias current optimized for avdd=2.5v 1x: lowest bias current, optimized for avdd=3.3v
wm8750jl production data w pd, april 2012, rev 4.1 50 register map register address (bit 15 ? 9) remarks bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default page ref r0 (00h) 0000000 left input volume livu linmute lizc linvol 010010111 19 r1 (01h) 0000001 right input volume rivu rinmute rizc rinvol 010010111 19 r2 (02h) 0000010 lout1 volume lo1vu lo1zc lout1vol[6:0] 001111001 32 r3 (03h) 0000011 rout1 volume ro1vu ro1zc rout1vol[6:0] 001111001 32 r4 (04h) 0000100 reserved 0 0 0 0 0 0 0 0 0 000000000 - r5 (05h) 0000101 adc & dac c ontrol adcdiv2 dacdiv2 a dcpol[1:0] hpor dacmu d eemph[1:0] adchpd 000001000 21, 26,29 r6 (06h) 0000110 reserved 0 0 0 0 0 0 0 0 0 000000000 - r7 (07h) 0000111 audio interface 0 bclkinv ms lrswap lrp wl[1:0] format[1:0] 000001010 42 r8 (08h) 0001000 sample rate bcm[1:0] clkdiv2 sr[4:0] usb 000000000 43, 44 r9 (09h) 0001001 reserved 0 0 0 0 0 0 0 0 0 000000000 - r10 (0ah) 0001010 left dac volume ldvu ldacvol[7:0] 011111111 27 r11 (0bh) 0001011 right dac volume rdvu rdacvol[7:0] 011111111 27 r12 (0ch) 0001100 bass control 0 bb bc 0 0 bass[3:0] 000001111 28 r13 (0dh) 0001101 treble control 0 0 tc 0 0 trbl[3:0] 000001111 28 r15 (0fh) 0001111 reset writing to this register resets all registers to their default state not reset - r16 (10h) 0010000 3d c ontrol 0 mode3d 3duc 3dlc 3ddepth[3:0] 3den 000000000 26 r17 (11h) 0010001 alc1 alcsel[1:0] maxgain[2:0] alcl[3:0] 001111011 24 r18 (12h) 0010010 alc2 0 alczc 0 0 0 hld[3:0] 000000000 24 r19 (13h) 0010011 alc3 0 dcy[3:0] atk[3:0] 000110010 24 r20 (14h) 0010100 noise gate 0 ngth[4:0] ngg[1:0] ngat 000000000 25 r21 (15h) 0010101 left adc volume lavu ladcvol[7:0] 011000011 22 r22 (16h) 0010110 right adc volume ravu radcvol[7:0] 011000011 22 r23 (17h) 0010111 additional control(1) tsden vsel[1:0] dmonomix[1:0] datsel[1:0] dacinv toen 011000000 18, 19, 29, 36 r24 (18h) 0011000 additional control(2) out3sw[1:0] hpswen hpswpol rout2inv tri lrcm adcosr dacosr 000000000 33, 34, 35, 42, 43, 49 r25 (19h) 0011001 pwr mgmt (1) vm idsel[1:0] vref ainl ainr a dcl adcr micb digenb 000000000 48 r26 (1ah) 0011010 pwr mgmt (2) dacl dacr lout1 rout1 lout2 rout2 mono out3 0 000000000 48 r27 (1bh) 0011011 additional control (3) adclrm[1:0] vroi hpflren 0 0 0 0 0 000000000 21, 34, 44 r31 (1fh) 0011111 adc input mode ds monomix[1:0] rdcm ldcm 0 0 0 0 000000000 17 r32 (20h) 0100000 adcl signal path 0 linsel[1:0] lmicboost[1:0] 0 0 0 0 000000000 17 r33 (21h) 0100001 adcr si gnal path 0 rinsel[1:0] rmic boost[1:0] 0 0 0 0 000000000 17 r34 (22h) 0100010 left out mix (1) ld2lo li2lo li2lovol[2:0] 0 lmixsel[2:0] 001010000 30 r35 (23h) 0100011 left out mix (2) rd2lo ri2lo ri2lovol[2:0] 0 0 0 0 001010000 30 r36 (24h) 0100100 right out mix (1) ld2ro li2ro li2rovol[2:0] 0 rmixsel[2:0] 001010000 31 r37 (25h) 0100101 right out mix (2) rd2ro ri2ro ri2rovol[2:0] 0 0 0 0 001010000 31 r38 (26h) 0100110 mono out mix (1) ld2mo li2mo li2movol[2:0] 0 0 0 0 001010000 31 r39 (27h) 0100111 mono out mix (2) rd2mo ri2mo ri2movol[2:0] 0 0 0 0 001010000 31 r40 (28h) 0101000 lout2 volume lo2vu lo2zc lout2vol[6:0] 001111001 33 r41 (29h) 0101001 rout2 volume ro2vu ro2zc rout2vol[6:0] 001111001 33 r42 (2ah) 0101010 monoout volume 0 mozc moutvol[6:0] 001111001 33
production data wm8750jl w pd, april 2012, rev 4.1 51 digital filter characteristics the adc and dac employ different digital filters. ther e are 4 types of digital filter, called type 0, 1, 2 and 3. the performance of types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. parameter test conditions min typ max unit adc filter type 0 (usb mode, 250fs operation) passband +/- 0.05db 0 0.416fs -6db 0.5fs passband ripple +/- 0.05 db stopband 0.584fs stopband attenuation f > 0.584fs -60 db adc filter type 1 (usb mode, 272fs or normal mode operation) passband +/- 0.05db 0 0.4535fs -6db 0.5fs passband ripple +/- 0.05 db stopband 0.5465fs stopband attenuation f > 0.5465fs -60 db high pass filter corner frequency -3db 3.7 hz -0.5db 10.4 -0.1db 21.6 dac filter type 0 (usb mode, 250fs operation) passband +/- 0.03db 0 0.416fs -6db 0.5fs passband ripple +/-0.03 db stopband 0.584fs stopband attenuation f > 0.584fs -50 db dac filter type 1 (usb mode, 272fs or normal mode operation) passband +/- 0.03db 0 0.4535fs -6db 0.5fs passband ripple +/- 0.03 db stopband 0.5465fs stopband attenuation f > 0.5465fs -50 db table 46 digital filter characteristics dac filters adc filters mode group delay mode group delay 0 (250 usb) 11/fs 0 (250 usb) 13/fs 1 (256/272) 16/fs 1 (256/272) 23/fs 2 (250 usb, 96k mode) 4/fs 2 (250 usb, 96k mode) 4/fs 3 (256/272, 88.2/96k mode) 3/fs 3 (256/272, 88.2/96k mode) 5/fs table 47 adc/dac digital filters group delay terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of t he frequency response in the pass-band region
wm8750jl production data w pd, april 2012, rev 4.1 52 dac filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 27 dac digital filter frequency response ? type 0 figure 28 dac digital filter ripple ? type 0 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 29 dac digital filter frequency response ? type 1 figure 30 dac digital filter ripple ? type 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 31 dac digital filter frequency response ? type 2 figure 32 dac digital filter ripple ? type 2
production data wm8750jl w pd, april 2012, rev 4.1 53 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 33 dac digital filter frequency response ? type 3 figure 34 dac digital filter ripple ? type 3 adc filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 35 adc digital filter frequency response ? type 0 figure 36 adc digital filter ripple ? type 0 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 37 adc digital filter frequency response ? type 1 figure 38 adc digital filter ripple ? type 1
wm8750jl production data w pd, april 2012, rev 4.1 54 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 39 adc digital filter frequency response ? type 2 figure 40 adc digital filter ripple ? type 2 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 41 adc digital filter frequency response ? type 2 figure 42 adc digital filter ripple ? type 3 de-emphasis filter responses -10 -8 -6 -4 -2 0 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) figure 43 de-emphasis frequency response (32khz) figure 44 de-emphasis error (32khz)
production data wm8750jl w pd, april 2012, rev 4.1 55 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) figure 45 de-emphasis frequency response (44.1khz) figure 46 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) figure 47 de-emphasis frequency response (48khz) figure 48 de-emphasis error (48khz) highpass filter the wm8750jl has a selectable digital highpass filter in the adc filter path to remove dc offsets. the filter response is characterised by the following polynomial: figure 49 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) =
wm8750jl production data w pd, april 2012, rev 4.1 56 applications information recommended external components 3 2 18 dbvdd dcvdd avdd linput1 28 rinput1 27 mode 29 csb 30 sdin 31 sclk 32 linput2 26 rinput2 25 linput3 24 rinput3 / hpdetect 23 bclk adclrc 9 daclrc 7 dacdat 6 adcdat 8 audio interface (i2s/lj/rj/dsp) 4 dgnd agnd 14 lout2 16 rout2 15 out3 lout1 13 rout1 12 micbias 22 vref 20 vmid 21 wm8750jl agnd + + agnd + agnd + c7 c16 c19 c20 c21 c17 c8 c9 c10 c11 c12 + c18 c14 c15 5 hpvdd dgnd agnd dgnd hpgnd 19 17 monoout 10 + c13 c4 c3 c2 c1 11 dvdd avdd mclk 1 control interface (2 or 3-wire) high for 3-wire low for 2-wire c6 dvdd + dgnd c5 + agnd avdd 8 ohm loudspeaker 16 or 32 ohm headphones 32 ohm ear speaker + - 10uf 10uf 100nf 100nf 1uf 1uf 1uf 1uf 1uf 1uf 10uf 10uf 1uf 100nf 100nf 100nf 100nf 220uf 220uf 100nf 10uf agnd 33 gnd_paddle layout notes: 1. c1 to c4, c16, c18 and c20 should be as close to the relative wm8750jl connecting pin as possible. 2. agnd and dgnd should be joined as close to the wm8750jl as possible. 3. c20 and c21 are only needed if micbias is used externally. 4. for capacitors c5, c6, c17, c19 and c21 it is recommended that low esr components are used. 5. for added strength and heat dissipation, it is recommended that the gnd_paddle (pin 33) is connected to agnd figure 50 recommended external components diagram
production data wm8750jl w pd, april 2012, rev 4.1 57 line input configuration when linput1/rinput1 or linput2/rinput2 are used as line inputs, the microphone boost and alc functions should normally be disabled. in order to avoid clipping, the user must ensur e that the input signal does not exceed avdd. this may require a potential divider circuit in some applications. it is also recommended to remove rf interference picked up on any cabl es using a simple first-or der rc filter, as high-frequency components in the input signal may otherwise caus e aliasing distortion in the audio band. ac signals with no dc bias should be fed to the wm8750j l through a dc blocking capacitor, e.g. 1 ? f. microphone input configuration figure 51 recommended circuit for line input for interfacing to a microphone, the alc function should be enabl ed and the microphone boost switched on. microphones held close to a speaker?s mouth would nor mally use the 13db gain setting, while tabletop or room microphones would need a 29db boost. the recommended application circuit is shown above. r1 and r2 form part of the biasing network (refer to microphone bias section). r1 connected to micbias is necessary only for electret type microphones that require a voltage bias. r2 shoul d always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. r1 and r2 should be large so as not to attenuate the si gnal from the microphone, which can have source impedance greater than 2kohm. c1 together with the source impedance of the microphone and the wm8750jl input impedance forms an rf filter. c2 is a dc blocking capacitor to allow the microphone to be biased at a different dc voltage to the micin signal. minimising pop noise at the analogue outputs to minimise any pop or click noise when the syst em is powered up or down, the following procedures are recommended. power up ? switch on power supplies. by default the wm8750jl is in standby mode, the dac is digitally muted and the audio interface, line outputs and headphone outputs are all off (dacmu = 1 power management registers 1 and 2 are all zeros). ? enable vmid and vref. ? enable dacs as required ? enable line and / or headphone output buffers as required. ? set dacmu = 0 to soft-un-mute the audio dacs. power down ? set dacmu = 1 to soft-mute the audio dacs. ? disable all output buffers. ? switch off the power supplies. r2 47kohm c1 220pf c2 1uf a gnd a gnd a gnd linput1/2/3 rinput1/2/3 from microphone r1 680 ohm to 2.2kohm check microphone's specification micbias
wm8750jl production data w pd, april 2012, rev 4.1 58 power management examples operation mode power manageme nt (1) power management (2) vref ainl/r pgas adcs dacs output buffers pgl pgr adl adr mbi dal dar lo1 ro1 lo2 ro2 mo hpd stereo headphone playback 1 0 0 0 0 0 0 1 1 1 1 0 0 0 x stereo line-in record 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 stereo microphone record 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 mono microphone record 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 stereo line-in to headphone out 1 1 0 0 0 0 0 0 0 1 1 0 0 0 x phone call 1 1 1 0 0 0 1 0 0 1 1 0 0 1 x speaker phone call [rout2inv = 1] 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 record phone call [l channel = mic with boost, r channel = rx, enable mono mix] 1 1 1 1 1 1 1 0 0 1 1 0 0 1 x table 48 register settings for power management
production data wm8750jl w pd, april 2012, rev 4.1 59 package dimensions dm101.a fl: 32 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch e2 b b 16 15 8 9 e c 0.08 c ccc a a1 c a3 seating plane 1 l index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e 1 17 24 25 32 d2 b c bbb m a 5 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vhhd-5. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to application note wan_0118 for further inform ation regarding pcb footprints and qfn package soldering. 7. this drawing is subject to change without notice. detail 1 a3 g t h w b exposed lead half etch tie bar dimensions (mm) symbols min nom max note a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.203 ref b d d2 e e2 e l 0.30 0.18 5.00 bsc 3.60 3.45 3.30 0.50 bsc 0.30 0.40 0.50 1 2 2 5.00 bsc 3.60 3.45 3.30 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vhhd-5. tolerances of form and position 0.25 h 0.1 0.20 g t 0.103 w 0.15 detail 1 detail 2 detail 2 exposed ground paddle 6 exposed ground paddle bottom view side view 0.30 45 m m
wm8750jl production data w pd, april 2012, rev 4.1 60 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any produc t or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its se lection and use of wolfson products . wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such in formation or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
production data wm8750jl w pd, april 2012, rev 4.1 61 revision history date rev originator changes 16/01/12 4.1 jmacd order codes updated fr om wm8750jlgefl and wm8750jlgefl/r to wm8750 c jlgefl and wm8750 c jlgefl/r to reflect change to copper wire bonding. 16/01/12 4.1 jmacd package diagram changed to dm101.a

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